FPGA FSPI Communication Demo

1 Demo overview

This demo runs Linux on the ARM side and performs a read/write test against the FPGA DRAM over the FSPI bus.

2 ARM-side and FPGA-side communication flow

ARM side implements the SPI Master function

  • Open the SPI device node: open the /dev/spidev4.0 device node.
  • Configure the FSPI bus: use ioctl commands to configure the FSPI bus polarity, phase, clock rate, and data length.
  • Select the transfer mode: you can choose single, dual, or quad mode. In quad mode, both sending and receiving use four lines. This demo supports quad mode only.
  • Data transfer: send data to the FSPI bus and read data from the FSPI bus.
  • Verify data: verify the transferred data, then print the read/write speed and bit error rate.

FPGA side implements the SPI Slave function

  • Data storage: the FPGA saves the data sent by the SPI Master to DRAM.
  • Data reading: when the SPI Master issues a read request, the FPGA reads the data from DRAM and transfers it to the SPI Master over the FSPI bus.

3 Procedure

Open a terminal and copy the executable smdt_spi_rw from this demo's bin directory (05-Development Materials\Software Development Materials\linux_demo\smdt_fpga_fspi_demo\bin) to the board's filesystem (the source code is available under the src path).

#修改 Linux 内核日志的显示级别，内核的日志级别被设置为只显示紧急或更高级别的消息
echo 1 4 1 7 > /proc/sys/kernel/printk

In the terminal, run the following commands to switch to the directory containing the smdt_fpga_fspi_demo executable.

#切换到 smdt_spi_rw 可执行程序所在目录
cd ‘可执行文件所在目录’

#查看 smdt_spi_rw 是否在该目录下
ls

If the executable smdt_spi_rw is in the current directory, change its permissions.

#修改文件权限
chmod 777 smdt_spi_rw

#查询是否修改成功
ls -ld smdt_spi_rw

After confirming the permission change succeeded, run ./smdt_spi_rw -h to view the program's help information.

#查看帮助信息
./smdt_spi_rw  -h

The result is shown below:

FPGA_FSPI_1

Functional test

Run the following command. On the ARM side, over the FSPI bus configured in quad mode, 2048 bytes of random data are written to the FPGA's DRAM, then read back for verification, and the FSPI bus read/write speed and the computed bit error rate are printed. The result is shown below.

./smdt_spi_rw -d /dev/spidev4.0 -s 150000000 -OH -m 3 -S 2048 -c 1

# 参数说明如下：

# `-d`：用于指定设备节点。

# `-s`：用于设置通信时钟的频率，单位是赫兹（Hz）。

# `-O`：表示时钟极性反转，即CPOL（Clock Polarity）设置为1。

# `-H`：表示在时钟周期开始时的第二个边沿采集数据，即CPHA（Clock Phase）设置为1。

# `-m`：选择传输模式，其中1代表单线模式，2代表双线模式，3代表四线模式。

# `-S`：设置传输数据的大小，单位是字节（Byte）。

# `-c`：设置循环传输数据包的次数。
FPGA_FSPI_2

As the figure shows, the measured write speed is 5.81 MB/s, the read speed is 10.5 MB/s, and the bit error rate is 0.00%.

Performance test

For the performance test, set the FSPI bus clock to 150MHz. Under this setting, the ARM writes 1MB of random data to the FPGA's DRAM over the FSPI bus, then reads it back, repeating this 100 times. No data verification is performed during the test; the FSPI read/write speed and error rate are reported at the end. The result is shown below. This demo writes 2048 bytes of random data per access to the FPGA DRAM, so the bit error rate is relatively high.

./smdt_spi_rw -d /dev/spidev4.0 -s 150000000 -OH -m 3 -S 1048576 -c 100
FPGA_FSPI_3