M.2 SSD
1 M.2 Interface Introduction
The M.2 interface is a physical interface standard that can support multiple different communication protocols, including:
- PCIe (Peripheral Component Interconnect Express)
- SATA (Serial Advanced Technology Attachment)
- USB (Universal Serial Bus)
Therefore, the speed and performance of the M.2 interface depend on the communication protocol and hardware implementation used. The M.2 interface can support PCIe 3.0, which is a high-speed data transfer protocol commonly used to connect graphics cards, solid-state drives (SSDs), and other devices that require high bandwidth.
In modern computers, especially in the consumer space, the most common and important application of the M.2 interface is to connect solid-state drives (SSDs). The "M.2 SSD" we usually refer to is mainly divided into two categories according to the protocol:
- The higher-performance NVMe protocol (running on the PCIe bus)
- The SATA protocol with performance comparable to traditional SATA hard drives
Simple Understanding
M.2 is the "slot and appearance", PCIe is the "highway", SATA is the "ordinary road", and NVMe is the "super traffic rule" running on the highway. Through the M.2 physical interface, we can choose which "road" and which set of "rules" the hard drive uses.
1.1 M.2 Slot Specifications
M.2 slots have different physical dimensions, including:
- 2242
- 2260
- 2280
- 22110
These numbers indicate the length and width of the slot.
1.2 RK3568 PCIe Architecture
The RK3568 chip has:
- 1 PCIe 3.0 x2 Lane Dual Mode controller
- 1 PCIe 3.0 x1 Lane RC Mode controller
- 1 PCIe 3.0 x2 Lane PHY
The PCIe 3.0 x2 Lane Dual Mode controller and the PCIe 3.0 x1 Lane RC Mode controller are both connected to the PCIe 3.0 x2 Lane PHY; that is, the two controllers share the same PHY.
The connection diagram is shown below:
2 Board Location of the M.2 Interface
Development board M.2 interface specifications:
- PCIe type: PCIe Gen3 x 2 lane
- Length specification: 2280
- Protocol support: this interface can only be used with M.2 NVMe protocol solid-state drives
3 M.2 SSD Usage — Command-Line Method
3.1 Device Tree File Explanation
Tips
The file path below: out/kernel/src_tmp/linux-5.10/arch/arm64/boot/dts/rockchip requires the kernel source to be compiled first.
The pins used by PCIe are dedicated pins; you only need to enable the corresponding controller, and the corresponding pins will be set to the corresponding modes.
Tips
Although this part of the DTS code is long, there are very few places that users need to modify — mainly changing the status property to okay. Therefore, this chapter does not analyze the DTS in detail; it only shows the key code and gives a brief explanation!
First, the base definition layer (rk3568.dtsi). Due to space limitations, only the code of the pcie30phy and pcie3x2 nodes is shown. Other nodes differ only in register addresses and the PHY used.
pcie30phy: phy@fe8c0000 {
compatible = "rockchip,rk3568-pcie3-phy";
reg = <0x0 0xfe8c0000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
<&cru PCLK_PCIE30PHY>;
clock-names = "refclk_m", "refclk_n", "pclk";
resets = <&cru SRST_PCIE30PHY>;
reset-names = "phy";
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
pcie3x2: pcie@fe280000 {
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <2>;
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
reg = <0x3 0xc0800000 0x0 0x400000>,
<0x0 0xfe280000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
/* rockchip,bifurcation; lane0 when using 1+1 */
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
};
};The above is the code of the pcie3x2 node. The three PCIe controllers provided by RK3568 are as follows:
- pcie2x1: PCIe 2.0 single-lane controller, register address 0xfe260000, uses combphy2_psq as the PHY
- pcie3x1: PCIe 3.0 single-lane controller, register address 0xfe270000, uses pcie30phy as the PHY, supports bifurcation mode
- pcie3x2: PCIe 3.0 dual-lane controller, register address 0xfe280000, uses pcie30phy as the PHY, supports bifurcation mode Each controller is configured with corresponding clock sources, interrupts, power domains, and reset signals. The default state is disabled.
Next, the pin configuration layer (rk3568-pinctrl.dtsi):
pcie20m0_pins: pcie20m0-pins {
rockchip,pins =
/* pcie20_clkreqnm0 */
<0 RK_PA5 3 &pcfg_pull_none>,
/* pcie20_perstnm0 */
<0 RK_PB6 3 &pcfg_pull_none>,
/* pcie20_wakenm0 */
<0 RK_PB5 3 &pcfg_pull_none>;
};
pcie30x1m0_pins: pcie30x1m0-pins {
rockchip,pins =
/* pcie30x1_clkreqnm0 */
<0 RK_PA4 3 &pcfg_pull_none>,
/* pcie30x1_perstnm0 */
<0 RK_PC3 3 &pcfg_pull_none>,
/* pcie30x1_wakenm0 */
<0 RK_PC2 3 &pcfg_pull_none>;
};
pcie30x2m0_pins: pcie30x2m0-pins {
rockchip,pins =
/* pcie30x2_clkreqnm0 */
<0 RK_PA6 2 &pcfg_pull_none>,
/* pcie30x2_perstnm0 */
<0 RK_PC6 3 &pcfg_pull_none>,
/* pcie30x2_wakenm0 */
<0 RK_PC5 3 &pcfg_pull_none>;
};Each PCIe controller provides multiple pin multiplexing modes (m0, m1, m2). Each configuration contains three key signals:
- clkreqn: clock request signal, used for power management
- perstn: reset signal, used for hardware reset control
- waken: wake-up signal, used to wake up from a low-power state
Finally, the board-level configuration layer (rk3568-evb6-ddr3-v10.dtsi)
&pcie30phy {
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&pcie20_3v3>;
status = "okay";
};
&pcie3x1 {
rockchip,bifurcation;
reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&pcie30_3v3>;
status = "okay";
};
&pcie3x2 {
rockchip,bifurcation;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&pcie30_3v3>;
status = "okay";
};- Enable PHY: the
&pcie30phynode setsstatus = "okay"to enable the PCIe 3.0 PHY - Configure reset GPIO: specifies the reset control pin via the
reset-gpiosproperty - Configure power supply: associates the 3.3V power regulator via the
vpcie3v3-supplyproperty - Enable bifurcation mode: for the PCIe 3.0 controllers, the lane bifurcation feature can be enabled via the
rockchip,bifurcationproperty - Enable the controller: set
status = "okay"to enable the corresponding PCIe controller
Caution
An SSD is different from a TF card — it does not support hot-plugging! Please make sure the system is powered off before installing the solid-state drive to avoid data loss.
The user needs to install the solid-state drive while powered off, and then boot the system.
3.2 Common Commands for Testing an M.2 SSD
After installing the SSD, use the same commands as for the TF card operation.
Use the following command to view the mount directory, then enter the mount directory to view files and operate via the command line.
df -h3.3 Functional Demonstration of M.2 SSD Usage
View the mount directory:
View the SSD contents:
After checking the mount directory with df -h, enter the mount directory to view files and perform command-line operations.