Pin Definitions

The data in this chapter must be verified line by line against the RK182X Datasheet pin table. The following is the template structure.

How are the GPIOs grouped?

RK182X GPIOs are grouped by port (GPIO0 ~ GPIOX), 32 pins per group:

Port	Pin range	Main multiplexed functions
GPIO0	PA0-PA31	I2C0, SPI0, UART0, JTAG
GPIO1	PB0-PB31	I2C1, SPI1, UART1, PWM
GPIO2	PC0-PC31	I2C2, SDMMC0, RMII, GMII
GPIO3	PD0-PD31	MIPI-CSI0, HDMI, I2S0
GPIO4	PE0-PE31	MIPI-CSI1, MIPI-DSI, I2S1
...	...	...

MIPI-CSI pin definitions?

Key pins: MIPI_CSI0_CLK_P/N (differential clock), MIPI_CSI0_D0~D3_P/N (4 data lane pairs), CAM0_RST (camera reset GPIO), CAM0_PWDN (power control), CAM0_MCLK (24MHz master clock).

Pin name	Type	Description
MIPI_CSI0_CLK_P/N	Differential input	MIPI clock lane 0
MIPI_CSI0_D0_P/N ~ D3_P/N	Differential input	MIPI data lanes 0-3
CAM0_RST	Output	Camera reset (GPIO)
CAM0_PWDN	Output	Camera power control
CAM0_MCLK	Output	Camera master clock (24MHz)

HDMI pin definitions?

Key pins: HDMI_TX_D0/D1/D2_P/N (3 TMDS data pairs), HDMI_TX_CLK_P/N (TMDS clock), HDMI_HPD (hot-plug detect input), HDMI_CEC (bidirectional control).

Pin name	Type	Description
HDMI_TX_D0_P/N	Differential output	TMDS data channel 0
HDMI_TX_D1_P/N	Differential output	TMDS data channel 1
HDMI_TX_D2_P/N	Differential output	TMDS data channel 2
HDMI_TX_CLK_P/N	Differential output	TMDS clock
HDMI_HPD	Input	Hot Plug Detect
HDMI_CEC	Bidirectional	CEC control

RMII/RGMII key pins: ETH_TXD0/TXD1 (transmit data), ETH_RXD0/RXD1 (receive data), ETH_TX_CLK/RX_CLK (clocks), ETH_TX_EN (transmit enable), ETH_RX_DV (receive valid), ETH_MDC/MDIO (MDIO management bus).

Pin name	Type	Description
ETH_TXD0/TXD1	Output	Transmit data
ETH_RXD0/RXD1	Input	Receive data
ETH_TX_CLK / RX_CLK	Clock	RMII mode
ETH_TX_EN	Output	Transmit enable
ETH_RX_DV	Input	Receive valid
ETH_MDC	Output	MDIO clock
ETH_MDIO	Bidirectional	MDIO data

What are the electrical characteristics?

Absolute maximum ratings: core voltage -0.3V~1.2V, IO 3.3V domain -0.3V~3.6V, IO 1.8V domain -0.3V~2.1V, storage temperature -40°C~125°C, junction temperature -40°C~105°C. Recommended operating conditions are in the table below. (Source: RK3588 Datasheet V2.0, §3.1, §3.2 — RK182X-specific electrical parameters need datasheet confirmation)

Absolute maximum ratings

Parameter	Min	Max	Unit
Core voltage VDD_CPU	-0.3	1.2	V
IO voltage VDD_IO (3.3V)	-0.3	3.6	V
IO voltage VDD_IO (1.8V)	-0.3	2.1	V
Storage temperature	-40	125	°C
Junction temperature	-40	105	°C

Recommended operating conditions

Parameter	Min	Typ	Max	Unit
VDD_CPU	0.72	0.9	1.0	V
VDD_NPU	0.72	0.9	1.0	V
VDD_DDR (LPDDR4X)	1.06	1.1	1.17	V
VDD_IO (3.3V)	3.0	3.3	3.6	V
Ambient temperature	-20	25	85	°C

(Source: RK182X Datasheet, electrical characteristics chapter)

PCB design notes?

DDR routing: length matching ±25mil, ±50mil between clock and data groups, ±5mil between differential pairs; MIPI routing: differential impedance 100Ω±10%, pair-to-pair spacing ≥3× trace width, length matching ±2mm, avoid 90° corners; power decoupling: 0.1µF next to every power pin plus bulk capacitance. (Source: RK182X PCB Layout Guide — needs verification)

DDR routing rules

All DDR signals length-matched within ±25 mil
Clock-to-data-group length difference within ±50 mil
Differential pair-to-pair length difference within ±5 mil
Intact reference planes; avoid crossing plane splits

MIPI routing rules

Differential impedance 100Ω ±10%
Pair-to-pair spacing ≥ 3× trace width
Length matching tolerance ±2 mm
Avoid 90° corners; use arcs or 45° bends

Power decoupling

Power domain	Decoupling capacitors	Placement
VDD_CPU	10×0.1µF + 2×10µF	Next to every power pin
VDD_NPU	10×0.1µF + 2×10µF	Next to every power pin
VDD_DDR	16×0.1µF + 4×10µF	Evenly spread over the DDR area
VDD_IO	4×0.1µF	Near the IO area

References: RK182X Datasheet; RK182X PCB Layout Guide